View ACE25Q400G_8361804.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 1 description the ACE25Q400G is 4 m - bit serial peripheral interface(spi) flash memory, and supports the dual/quad spi: serial clock, chip select, serial data i/o0 (si), i/o1 (so), i/o2 (/wp), and i/o3 (/hold). the dual i/o data is transferred with speed of 2 16m bits/s and the quad i/o & quad output data is transferred with speed of 43 4m bits/s. the device uses a single low voltage power supply, ranging from 2.7 volt to 3.6 volt. additionally, the device supports jedec standard manufacturer and device id and thr ee 256 - bytes security registers. features serial peripheral interface (spi) - standard spi: sclk, /cs, si, so, /wp, /hold - dual spi: sclk, /cs, io0, io1, /wp, /hold - quad spi: sclk, /cs, io0, io1, io2, io3 read - normal read (serial): 50mhz clock r ate - fast read (serial): 108mhz clock rate - dual/quad (multi - i/o) read: 108mhz clock rate program - serial - input page program up to 256bytes - program suspend and resume erase - block erase (64/32 kb) - sector erase (4 kb) - chip erase - erase suspe nd and resume program/erase speed - p age pr o gr a m ti m e: 0 . 7ms t y p i cal - sector erase time: 60ms typical - block erase time: 0.3/0.5s typical - chip erase time: 4 s typical flexible architecture - sector of 4k - byte - block of 32/64k - byte low power co nsumption - 20ma maximum active current - 5ua maximum power down current
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 2 software/hardware write protection - 3x256 - byte security registers with otp lock - enable/disable protection with wp pin - write protect all /portion of memory via software - top or bottom, sector or block selection single supply voltage - full voltage range: 2.7~3.6v temperature range - commercial (0 to +70 ) - industrial ( - 40 to +85 ) cycling endurance/data retention - typical 100k program - erase cycles on any sector - t ypical 20 - year data retention at +55 packaging type
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 3 signal description during all operations, vcc must be held stable and within the specified valid range: vcc(min) to vcc(max). all of the input and output signals must be held high or low (according to voltages of vih, voh, vil or vol, see section 8.6, dc electrical characte ristics on page 40 ). these signals are signal names table 1 pin no pin name i/o description 1 /cs i chip select 2 so (io1) i/o serial output for single bit da ta instructions. io1 for dual or quad instructions. 3 /wp (io2) i/o write protect in single bit or dual data instructions. io2 in quad mode. the signal has an internal pull - up resistor and may be left unconnected in the host system if not used for quad i nstructions. 4 vss ground 5 si (io0) i/o serial input for si ngle bit data instructions. io0 for dual or quad instructions. 6 sclk i serial clo ck 7 / hold# (io3) i/o hold (pause) serial transfer in single bit or dual data instructions. io3 in quad - i/o m ode. the signal has an internal pull - up resistor and may be left unconnected in the host system if not used for quad instructions. 8 vcc core and/ o power supply ordering information ace25q 400 g ua8 + x h u: tube t: tape and reel pb - free ua8: uson8 3*2 ( 0.75 - 0.50mm ) halogen - free 4 00: 4 m bit
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 4 chip select (/cs) the chip select signal indicates when a instruction for the device is in process and the other signals are relevant for the memory device. when the /cs signal is at the logic high state, the device is not selected and all input signals are ignored and all output signals are high impedance. unless an internal program, erase or write status registers embedded operation is in progress, the device will be in the standby power mode. driving the /cs input to logic low state enables the device, placing it in the active power mode. after power up, a falling edge on /cs is required prior to the start of any instruction. serial clock (sclk) this input signal provides the synchronization reference for the spi interface. instructions, addresses, or data input are latc hed on the rising edge of the sclk signal. data output changes after the falling edge of sclk. serial input (si)/io0 this input signal is used to transfer data serially into the device. it receives instructions, addresses, and data to be programmed. value s are latched on the rising e dge of serial sck clock signal. si becomes io0 an input and output during dual and quad instructions for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial sck clock signal) as well as shifting out data (on the falling edge of sck). serial data output (so)/io1 this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of the serial sck clock signal. so becomes io1 an input an d output during dual and quad instructions for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial sck clock signal) as well as shifting out data (on the falling edge of sck). write protect (/wp)/io2 when /wp is driven low (vil), while the status register protect bits (srp1 and srp0) of the status registers (sr2[0] and sr1[7]) are set to 0 and 1 respectively, it is not possible to write to the status registers. this prevents any alteration of the status reg isters. as a consequence, all the data bytes in the memory area that are protected by the block protect, tb, sec, and cmp bits in the status registers, are also hardware protected against data modification while /wp remains low. the /wp function is not ava ilable when the quad mode is enabled (qe) i n status register 2 (sr2[1]=1). the /wp function is replaced by io2 for input and output during quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the sck signal) as well as shifting out data (on the falling edge of sck). /wp has an internal pull - up resistance; when unconnected; /wp is at vih and may be left unconnected in the host system if not used for quad mode.
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 5 hold (/hold)/io3 the /hold signal goes low to s top any serial communications wi th the device, but doesn?t stop the operation of write status register, progr amming, or erasing in progress. the operation of hold, need /cs keep low, and starts on falling edge of the /hold signal, with sclk signal being lo w (if sclk is not being low, hold operation will not start until sclk being low). the hold condition ends on rising edge of /hold signal with sclk being low (if sclk is not being low, hold operation will not end until sclk being low). the hold condition st arts on the falling edge of the hold (/hold) signal, provided that this coincides with sck being at the logic low state. if the falling edge does not coincide with the sck signal being at the logic low state, the hold condition starts whenever the sck sign al reaches the logic low state. taking the /hold signal to the logic low state does not terminate any write, program or erase operation that is currently in progress. vcc power supply vcc is the supply voltage. is the single voltage used for all device f unctions including read, program, and erase. vss ground vss is the reference for the vcc supply voltage.
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 6 uniform block sector architecture table 2 ACE25Q400G block/sector addresses m e mory d e ns it y b l o c k ( 6 4 kb y t e) b l o c k ( 3 2 kb y t e) sec t or n o . sec t or s i ze ( kb ) a d d ress ra n ge 4 m k b it blo c k 0 h a lf b l o ck 0 sect o r 0 4 000 0 00 h - 00 0 f f fh 007 0 00 h - 00 0 f f fh sect o r 7 4 h a lf b l o ck 1 sect o r 8 4 008 0 00 h - 00 8 f f fh 4 sect o r 15 4 000 0 00 h - 00 0 f f fh blo c k1 h a lf b l o ck 2 sect o r 16 4 010 0 00 h - 01 0 f f fh s ect o r 23 4 017 0 00 h - 017f f fh h a lf b l o ck 3 sect o r 24 4 018 0 00 h - 018f f fh sect o r 31 4 01f 0 00 h - 0 1f f f fh blo c k 2 h a lf b l o ck 12 sect o r 96 4 0 6 0 0 00 h - 0 6 0f f fh sect o r 103 4 0 6 7 0 00 h - 0 6 7f f fh h a lf b l o ck 13 sect o r 104 4 0 6 8 0 00 h - 0 6 8f f fh sect o r 111 4 0 6 f 0 00 h - 0 6 ff f fh blo c k 3 h a lf b l o ck 14 sect o r 112 4 0 7 0 0 00 h - 0 7 0f f fh sect o r 119 4 0 7 7 0 00 h - 0 7 7f f fh h a lf b l o ck 15 sect o r 120 4 0 7 8 0 00 h - 0 7 8f f fh sect o r 127 4 0 7 f 0 00 h - 0 7 ff f fh notes: 1. block = uniform block, a nd the size is 64k bytes. 2. half block = half uniform block, and the size is 32k bytes. 3. sector = uniform sector, and the size is 4k bytes.
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 7 device operation standard spi instructions the ACE25Q400G features a serial peripheral interface on 4 signals bus: serial clock (sclk), chip select (/cs), serial data input (si) and serial data output (so). both spi bus mode 0 and 3 are supported. input data is latched on the rising edge of sclk and data shifts out on the falling edge of sclk. dual spi i nstructions the ACE25Q400G supports dual spi operation when using the ?dual output fast read? and ?dual i/o fast read? (3bh and bbh) instructions. these instructions allow data to be transferred to or from the device at two times the rate of the standard s pi. when using the dual spi instruction the si and so pins become bidirectional i/o pins: io0 and io1. quad spi instructions the ACE25Q400G supports quad spi operation when using the ?quad output fast read?, ?quad i/o fast read? (6bh, ebh) instructions. t hese instructions allow data to be transferred t - o or from the device at four times the rate of the standard spi. when using the quad spi instruction the si and so pins become bidirectional i/o pins: io0 and io1, and /wp and /hold pins become io2 and io3. quad spi instructions require the non - volatile quad enable bit (qe) in status register - 2 to be set . operation features supply voltage operating supply voltage prior to selecting the memory and issuing instructions to it, a valid and stable vcc voltage wit hin the specified [vcc(min), vcc(max)] range must be applied (see operating ranges of page 3 9 ). in order to secure a stable dc supply voltage, it is recommended to decouple the vcc line with a suitable capacitor (usually of the order of 10nf to 100nf) clos e to the vcc/vss package pins. this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tw). power - up conditions when the power supply is turned on, vcc rises continuously from vss to vcc. during this time, the chip select (/cs) line is not allowed to float but should follow the vcc voltage, it is therefore recommended to connect the /cs line to vcc via a suitable pull - up resistor. in addit ion, the chip select (/cs) input offers a built - in safety feature, as the /cs input is edge sensitive as well as level sensitive: after power - up, the device does not become selected until a falling edge has first been detected on chip select (/cs). this en sures that chip select (/cs) must have been high, prior to going low to start the first operation. device reset in order to prevent inadvertent write operations during power - up (continuous rise of vcc), a power on reset (por) circuit is included. at power - up, the device does not respond to any instruction until vcc has reached the power on reset threshold voltage (this threshold is lower than the minimum vcc operating voltage defin e d in operating ranges of page 3 9 ) . when vcc has passed the por threshold, t he device is reset.
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 8 power - down at power - down (continuous decrease in vcc), as soon as vcc drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any instruction sent to it. during power - down, the device must be deselected (chip select (/cs) should be allowed to follow the voltage applied on vcc) and in standby power mode (that is there should be no internal write cycle in progress). active power and standby power modes when chip select (/cs) i s low, the device is selected, and in the active power mode. the device consumes icc. when chip select (/cs) is high, the device is deselected. if a write cycle is not currently in progress, the device then goes in to the standby power mode, and the device consumption drops to icc1. hold condition the hold (/hold) signal is used to pause any serial communications with the device without resetting the clocking sequence. during the hold condition, the serial data output (so) is high impedance, and serial dat a input (si) and serial clock (sclk) are don t care. to enter the hold condition, the device must be selected, with chip select (/cs) low. normally, the device is kept selected, for the whole duration of the hold condition. deselecting the device while it is in the hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any proce sses that had been in progress. the hold condition starts when the hold (/hold) signal is driven low at the sa me time as serial clock (sclk) already being low (as shown in figure 1) the hold condition ends when the hold (hold) signal is driven high at the same time as serial clock (c) already being low. al so shows what happens if the rising and falling edges are not timed to coincide with serial clock (sclk) being low. figure 1 hold condition activation figure 1
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 9 status register status register table s ee table 3 and table 4 f or detail description of the status register bits. status register - 2 (s r2) and status register - 1 (sr1) can be used to provide status on the availability of the flash memory array, if the device is write enabled or disabled the state of write protection, quad spi setting, security register lock status, and erase/program suspen d status. table 3 status register - 2 (sr2) b i t n a m e f u nc ti o n d ef a ult v a l ue d e s cr i pt i o n 7 sus suspend status 0 0 = erase/program not suspended 1 = erase/program suspended 6 cmp complement protect 0 0 = normal protection map 1 = inverted protection map 5 lb3 security register lock bits 0 otp lock bits 3:1 for security registers 3:1 0 = security register not protected 4 lb2 0 3 lb1 0 2 reserved reserved 0 1 qe quad enable 0 0 = quad mode not enabled, the /wp pin and /hold are enabled. 1 = quad m ode enabled, the io2 and io3 pins are enabled, and /wp and /hold functions are disabled 0 srp1 status resister protect 1 0 0 = srp0 selects whether /wp input has effect on protection of the status register 1 = srp0 selects power supply lock down or otp l ock down mode
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 10 table 4 s t a t us r eg i s t e r - 1 ( s r 1) b i t n a m e function d ef a ult v a l ue d e s cr i pt i o n 7 srp0 status resister protect 0 0 0 = /wp input has no effect or power supply lock down mode 1 = /wp input can protect the status register or otp lock down 6 sec sector/block protect 0 0 = bp2 - bp0 protect 64kb blocks 1 = bp2 - bp0 protect 4kb sectors 5 tb top/bottom protect 0 0 = bp2 - bp0 protect from the top down 1 = bp2 - bp0 protect from the bottom up 4 bp2 block protect bits 0 000b = no protection see tabl e 6 and table 7 for protection ranges 3 bp1 0 2 bp0 0 1 wel write enable latch 0 0 = not write enabled, no embedded operation can start 1 = write enabled, embedded operation can start 0 wip write in progress status 0 0 = not busy, no embedded opera tion in progress 1 = busy, embedded operation in progress t h e s t at u s a n d c o n t r ol b it s wip bit the write in progress (wip) bit indicates whether the memory is busy in program/erase/write status register progress. when wip bit sets to 1, means the device i s busy in program/erase/write status register progress, when wip bit sets 0, means the device is not in program/erase/write status register progress. wel bit the write enable latch bit indicates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write status register, program or erase instruction is accepted. sec, tb, bp2, bp1, bp0 bits the block protect (sec, tb, bp2, bp1, bp0) bits are non - vol atile. they define the size of the area to be software protected against program and erase instructions. these bits are written with the write status register instructio n. when the block protect (sec, tb, bp2, bp1, bp0) bits are set to 1, the relevant memor y area (as defined in table 6).becomes protected against page program, sector erase and block erase instructions. the block protect (sec, tb, bp2, bp1, bp0) bits can be written provided that the hardware protected mode has not been set.
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 11 srp1, srp0 bits the status register protect (srp1 and srp0) bits are non - volatile read/write bits in the status register. the srp bits control the method of write protection: software protection, hardware protection, power supply lock - down or one time programmable protec tion. qe bit the quad enable (qe) bit is a non - volatile read/write bit in the status register that allows quad operation. when the qe bit is set to 0 (default) the /wp pin and /hold pin are enable. when the qe pin is set to 1, the quad io2 and io3 pins are enabled. (the qe bit should never be set to 1 during standard spi or dual spi operation if the /wp or /hold pins directly to the power supply or ground). lb3/lb2/lb1 bit the lb bit is a non - volatile one time program (otp) bit in status register that provi de the write protect control and status to the security registers. the default state of lb is 0, the security registers are unlocked. lb can be set to 1 individually using the write register instruction. lb is one time programmable, once it?s set to 1, the 256byte security registers will become read - only permanently, lb3/2/1 for security registers 3:1. cmp bit the cmp bit is a non - volatile read/write bit in the status register2 (bit6). it is used in conjunction the sec - bp0 bits to provide more flexibility f or the array protection. please see the status registers memory protection table for details. the default setting is cmp=0. sus bit the sus bit is a read only bit in the status register2 (bit7) that is set to 1 after executing an erase/program suspend (75h ) instruction. the sus bit is cleared to 0 by erase/program resume (7ah) instruction as well as a power - down, power - up cycle. status register protect table ( table5 ) s r p1 s r p0 / wp s t at u s r e gis t er d e s cr i pt i o n 0 0 x software protected the status register c an be written to after a write enable instruction, wel=1.(factory default) 0 1 0 hardware protected /wp=0, the status register locked and cannot be written. 0 1 1 hardware unprotected /wp=1, the status register is unlocked and can be written to after a write enable instruction, wel=1. 1 0 x power supply lock - down (1) status register is protected and cannot be written to again until the next power - down, power - up cycle. 1 1 x one time program (2) status regist er is permanently protected and can not be writt en to. notes: 1. when srp1, srp0= (1, 0), a power - down, power - up cycle will cha nge srp1, srp0 to (0, 0) state. 2. the one time program feature is available upon special order. please contact ace for details.
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 12 write protect features 1. software protec tion: the block protect (sec, tb, bp2, bp1, bp0) bits define the section of the memory array that can be read but not change. 2. hardware protection: /wp going low to protected the bp0~sec bits an d srp0~1 bits. 3. deep power - down: in deep power - down mode, al l inst ructions are ignored except the release from de ep power - down mode instruction. 4. write enable: the write enable latch (wel) bit must be set prior to every page program, sector erase, block erase, chip erase, write status register and erase/program se curity registers instruction. status register memory protection protect table table 6 ACE25Q400G status register memory protection (cmp=0) status register content memory content s e c tb b p 2 b p 1 b p 0 b l o c ks a d d ress e s d e ns it y por ti o n x x 0 0 0 n o n e n o n e n o n e n o n e 0 0 0 0 1 7 0 7 0 0 0 0 h - 0 7 f f f fh 64k b upper 1/ 8 0 0 0 1 0 6 and 7 0 6 0 0 0 0 h - 0 7 f f f fh 128k b upper 1/ 4 0 0 0 1 1 4 to 7 0 4 0 000 h - 0 7 f f f f h 256k b upper 1/ 2 0 1 0 0 1 0 0000 0 0 h - 0 0 f f f f h 64k b lower 1/ 8 0 1 0 1 0 0 and 1 000 000 h - 0 1 f f f f h 128k b lower 1/ 4 0 1 0 1 1 0 to 3 000 000 h - 0 3 f f f f h 256k b lower 1/ 2 0 x 1 x x 0 to 7 000 000 h - 0 7 f f f f h 512k b all 1 0 0 0 1 7 0 7 f 000 h - 0 7 f f f f h 4 k b upper 1/ 128 1 0 0 1 0 7 0 7 e 000 h - 0 7 f f f f h 8 k b upper 1/ 64 1 0 0 1 1 7 0 7 c 000 h - 0 7 f f f f h 16k b upper 1 /32 1 0 1 0 x 7 0 7 8 000 h - 0 7 f f f f h 32k b uppe r 1/ 16 1 0 1 1 0 7 0 7 8 000 h - 0 7 f f f f h 32kb upper 1/ 16 1 1 0 0 1 0 0000 0 0 h - 0 0 f f f f h 4 k b lower 1/ 128 1 1 0 1 0 0 000 000 h - 0 0 1 f f f h 8 k b lower 1/ 64 1 1 0 1 1 0 0000 0 0 h - 0 3f f f f h 16kb lower 1/ 32 1 1 1 0 x 0 0000 0 0 h - 0 0 7 f f f h 32kb lower 1/ 16 1 1 1 1 0 0 0000 0 0 h - 0 0 7 f f f h 32k b lower 1/ 16 1 x 1 1 1 0 to 7 0000 0 0 h - 0 7 f f f f h 512kb all
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 13 table 7 ACE25Q400G status register memory protection (cmp=1) status register content memory content s e c tb b p 2 b p 1 b p 0 b l o c ks a d d ress e s d e ns it y por ti o n x x 0 0 0 0 to 7 0000 0 0 h - 0 07f f fh 5 12k b all 0 0 0 0 1 0 to 6 0 0 0 0 0 0 h - 0 6 f f f fh 448k b lower 7/8 0 0 0 1 0 0 to 5 000 0 0 0 h - 0 5 f f f fh 384kb lower 3/4 0 0 0 1 1 0 to 3 0000 0 0 h - 0 3f f f f h 256kb lower 1/2 0 1 0 0 1 1 to 7 0 1 0000 h - 0 7 f f f f h 448kb upper 7/8 0 1 0 1 0 2 to 7 0 2 0000 h - 0 7 f f f f h 384kb upper 3 /4 0 1 0 1 1 4 to 7 0 4 0000 h - 0 7 f f f f h 256kb upper 1/2 0 x 1 x x n o n e n o n e n o n e n o n e 1 0 0 0 1 0 to 7 0000 0 0 h - 0 07f f fh 508kb lower 127/128 1 0 0 1 0 0 to 7 0000 0 0 h - 0 07d f fh 504kb lower 63/64 1 0 0 1 1 0 to 7 0000 0 0 h - 0 07 b f fh 496kb lower 31/32 1 0 1 0 1 0 t o 7 0000 0 0 h - 0 07 7 f fh 480kb lower 15/16 1 0 1 1 x 0 to 7 0000 0 0 h - 0 07 7 f fh 480kb lower 15/16 1 1 0 0 0 0 to 7 0 010 0 0 h - 0 7f f f fh 508kb upper 127/12/ 1 1 0 1 1 0 to 7 0 0 2 0 0 0 h - 0 7f f f fh 504kb upper 63/64 1 1 0 1 0 0 to 7 0 0 4 0 0 0 h - 0 7f f f fh 496kb upper 31/32 1 1 1 x 1 0 to 7 0 0 8 0 0 0 h - 0 7f f f fh 480kb upper 15/16 1 1 1 x x 0 to 7 0 0 8 0 0 0 h - 0 7f f f fh 480kb upper 15/16 1 x 1 1 x n o n e n o n e n o n e n o n e
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 14 device identification three legacy instructions are supported to access device identification that can indicate th e manufacturer, device type, and capacity (density). the returned data bytes provide the information as shown in the below table. table 8 ACE25Q400G id definition table o pera ti o n c o d e m 7 - m0 i d 1 5 - i d 8 i d 7 - id0 9 f h e0 40 13 90h e0 12 a b h 12 instructio ns description all instructions, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of sclk after /cs is driven low. then, the one byte instruction code must be shifted in to the device , most significant bit first on si, each bit being latched on the rising edges of sclk. see table 9 , every instruction sequence starts with a one - byte instruction code. depending on the instruction, this might be followed by address bytes, or by data byte s, or by both or none. /cs must be driven high after the last bit of the instruction sequence has been shifted in. for the instruction of read, fast read, read status register or release from deep power down, and read device id, the shifted - in instruction sequence is followed by a data out sequence. /cs can be driven high after any bit of the data - out sequence is being shifted out. for the instruction of page program, sector erase, block erase, chip erase, write status register, write enable, write disable or deep power - down instruction, /cs must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. that is /cs must driven high when the number of clock pulses after /cs being driven low is an exact multiple of eight. for page program, if at any time the input byte is not a full byte, nothing will happen and wel will not be reset.
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 15 i ns tr uc t i o n set ta b l e 9 i ns t ruct io n n ame b y t e 1 b y t e 2 b y t e 3 b y t e 4 b y t e 5 b y t e 6 write enable 06h write disable 04h read status register - 1 05h (s7 - s0) read status register - 2 35h (s15 - s8) write enable for volatile status register 50h write status register 01h (s7 - s0) (s15 - s8) read data 03h a23 - a16 a15 - a8 a7 - a0 (d7 - d0) next byte fast read 0bh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) dual output fast read 3bh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0)(1) dual i/o fast read bbh a23 - a8 (2) a7 - a0 m7 - m0 (2) (d7 - d0) (1) quad output fast read 6bh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0)(3) quad i/o fast read ebh a23 - a0 m 7 - m0 (4) dummy (d7 - d0) (5) set burst with wrap 77h dummy dummy dummy w8 - w0 continuous read reset ffh ffh page program 02h a23 - a16 a15 - a8 a7 - a0 (d7 - d0) next byte sector erase 20h a23 - a16 a15 - a8 a7 - a0 block erase(32k) 52h a23 - a16 a15 - a8 a7 - a0 block erase(64k) d8h a23 - a16 a15 - a8 a7 - a0
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 16 i ns t ruct io n n ame b y t e 1 b y t e 2 b y t e 3 b y t e 4 b y t e 5 b y t e 6 chip erase c7/60h program/erase suspend 75h program/erase resume 7ah deep power - down b9h release from deep power - down, and r ead device id abh dummy dummy dummy (id7 - id0) release from deep power - down abh manufacturer/ device id 90h dummy dummy 00h (m7 - m0) (id7 - id0) jedec id 9fh (m7 - m0) (id15 - id8) (id7 - id0) erase security registers (6) 44h a23 - a16 a15 - a8 a7 - a0 progr am security registers (6) 42h a23 - a16 a15 - a8 a7 - a0 (d7 - d0) (d7 - d0) read security registers(6) 48h a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) enable reset 7eh reset device 99h
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 17 no te s: 1. d u a l o u t put da t a io 0 = ( d6, d4, d2, d 0) io 1 = ( d7, d5, d3, d 1) 2. d u a l i nput a d dress io 0 = a22, a20, a18, a16, a14, a12, a10, a8, a6, a4, a2, a0, m 6, m 4, m 2, m 0 io 1 = a23, a21, a19, a17, a15, a13, a11, a9, a7, a5, a3, a1, m 7, m 5, m 3 3. q uad o u t put d a t a io 0 = ( d 4, d 0 , ..) io 1 = ( d 5, d 1 , ..) io 2 = ( d 6, d 2 , . . ) io3 = (d7, d3,..) 4. q uad i nput a d dress io 0 = a20, a16, a12, a 8, a4, a0, m 4, m 0 io 1 = a21, a17, a13, a 9, a5, a1, m 5, m 1 io 2 = a22, a18, a14, a 10, a6, a2, m 6, m 2 io3 = a23, a19, a15, a11, a7, a3, m7, m3 5. fast r e ad q u a d i/o d a t a io 0 = ( x, x, x, x, d 4, d 0 , ) io 1 = ( x, x, x, x, d 5, d 1 , ) io 2 = ( x, x, x, x, d 6, d 2 , ) io 3 = ( x, x, x, x, d 7, d 3 , ) 6. secu r i t y r egi s t ers a d dress: se c urity r e g i s t er0: a 2 3 - a 16=0 0 h, a1 5 - a8 = 0 0 h, a 7 - a0= b y t e addr e ss; se c urity r e g i s t er1: a 2 3 - a 16=0 0 h, a1 5 - a8 = 0 1 h, a 7 - a0= b y t e addr e ss; se c urity r e g i s t er2: a 2 3 - a 16=0 0 h, a1 5 - a8 = 0 2 h, a 7 - a0= b y t e addr e ss; se c urity r e g i s t er3: a 2 3 - a 16=0 0 h, a1 5 - a8 = 0 3 h, a 7 - a0= b y t e addr e ss; se c urity r e g i s t er 0 can b e used t o s t ore t he f l a sh d i sco v era b l e par a m e t e r s, the f ea t ure i s u p on s p ec i a l orde r , p l e ase c o n t act ace f o r de t a i l s.
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 18 configuration and status instructions write enable (06h) see figure 2 , t he write enable instruction is for setting the write enable latch bit. the write enable latch bit must be set prior to every page program, sector erase, block erase, chip erase and write status register instruction. the write enable instruction sequence: /cs goes low sending the write enable instruction /cs goes high. figure 2 write enable sequence diagram figure 2 write disable (04 h) see figure 3, t he write disable instruction is for resetting the write enable latch bit. the write disable instruction sequence: /cs goes low sending the write disable instruction /cs goes high. the wel bit is reset by following condition: power - up and upon completion of the write status register, page program, sector erase, block erase and chip erase instructions. figure 3, write disable sequence diagram figure 3
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 19 re ad status register (05h or 35h) see figure 4, t he read status register (rdsr ) instruction is for reading the status register. the status register may be read at any time, even while a program, erase or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progr ess (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuously. for instruction code ?05h?, the so will output status register bits s7~s0. the instruction code ?35h?, the so will output status reg ister bits s15~s8. figure 4 . read s tatus register sequence diagram figure 4 write status register (01h) see figure 5, t he write status register instruction allows new values to be written to the status register. before it can be accepted, a write e nable instruction must previously have been executed. after the write enable instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register instruction has no effect on s15, s1 and s0 of the status regist er. /cs must be driven high after the eighth or sixteen bit of the data byte has been latched in. if not, the write status register instruction is not executed. if /cs is driven high after eighth bit of the data byte, the qe and srp1 bits will be cleared t o 0. as soon as /cs is driven high, the self - timed write status register cycle (whose duration is tw) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip ) bit. the write in progress (wip) bit is 1 during the self - timed write status register cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch is reset. the write status register instruction allows the user to change the values of the block protect (sec, tb, bp2, bp1, bp0) bits, to define the size of the area that is to be treated as read - only, as defined in table 3. the write status register instruction also allows the user to set or reset the status register protect (srp 1 and srp0) bits in accordance with the write protect (/wp) signal. the status register protect (srp1 and srp0) bits and write protect (/wp) signal allow the device to be put in the hardware protected mode. the write status register instruction is not exec uted once the hardware protected mode is entered. figure 5 write status register sequence diagram figure 5
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 20 write enable for volatile status register (50h) see figure 6, t he non - volatile status register bits can also be written to as volatile bit s. during power up reset, the non - volatile status register bits are copied to a volatile version of the status register that is used during device operation. this gives more flexibility to change the system configuration and memory protection schemes quick ly without waiting for the typical non - volatile bit write cycles or affecting the endurance of the status register non - volatile bits. to write the volatile version of the status register bits, the write enable for volatile status register (50h) instruction must be issued prior to each write status registers (01h) instruction. write enable for volatile status register instruction will not set the write enable latch bit, it is only valid for the next following write status registers instruction, to change the volatile status register bit values. figure 6 write enable for volatile status register figure 6 read instructions read data (03h) see figure 7 , the read data bytes (read) instruction is followed by a 3 - byte address (a23 - a0), each bit being latch ed - in during the rising edge of sclk. then the memory content, at that address, is shifted out on so, each bit being shifted out, at a max frequency fr, during the falling edge of sclk. the address is automatically incremented to the next higher address af ter each byte of data is shifted out allowing for a continuous stream of data. this means that the entire memory can be accessed with a single command as long as the clock continues. the command is completed by driving /cs high. the whole memory can be rea d with a single read data bytes (read) instruction. any read data bytes (read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. normal read mode running up to 50mhz . figure 7 read data bytes sequence diagram figure 7
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 21 fast read (0bh) see figure 8, t he read data bytes at higher speed (fast read) instruction is for quickly reading data out. it is followed by a 3 - byte address (a23 - a0) and a dummy byte, each bi t being latched - in during the rising edge of sclk. then the memory content, at that address, is shifted out on so, each bit being shifted out, at a max frequency fc, during the falling edge of sclk. the first byte addressed can be at any location. the addr ess is automatically incremented to the next higher address after each byte of data is shifted out. figure 8 fast read sequence diagram figure 8 dual output fast read (3bh) see figure 9, t he dual output fast read instruction is followed by 3 - byte address (a23 - a0) and a dummy byte, each bit being latched in during the rising edge of sclk, then the memory contents are shifted out 2 - bit per clock cycle from si and so. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. figure 9 dual output fast read sequence diagram figure 9
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 22 quad output fast read (6bh) see figure 10, t he quad output fast read instruction is followed by 3 - byte a ddress (a23 - a0) and a dummy byte, each bit being latched in during the rising edge of sclk, then the memory contents are shifted out 4 - bit per clock cycle from io3, io2, io1 and io0. the first byte addressed can be at any location. the address is automatic ally incremented to the next higher address after each byte of data is shifted out. figure 10 quad output fast read sequence diagram figure 10 dual i/o fast read (bbh) see figure 11, t he dual i/o fast read instruction is similar to the dual output fast read instruction but with the capability to input the 3 - byte address (a23 - 0) and a ?continuous read mode? byte 2 - bit per clock by si and so, each bit being latched in during the rising edge of sclk, then the memory contents are shifted out 2 - bi t per clock cycle from si and so. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. figure 11 dual i/o fast read sequence diagram (initial command o r previous m5 - 4 10) figure 11
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 23 dual i/o fast r ead with ?continuous read mode? t he fast read dual i/o command can further reduce instruction overhead through setting the ?continuous read mode? bits (m7 - 0) after the input address bits (a23 - 0), as shown in fig ure 14. the upper nibble of the (m7 - 4) controls the length of the next fast read dual i/o command through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3 - 0) are don?t care (?x?). however, the io pins should b e high - impedance prior to the falling edge of the first data out clock. if the ?continuous read mode? bits m5 - 4 = (1,0), then the next fast read dual i/o command (after /cs is raised and then lowered) does not require the bbh instruction code, as shown in figure 1 2 . this reduces the command sequence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the ?continuous read mode? bits m5 - 4 do not equal to (1,0), the next command (after /cs is raised and then lowe red) requires the first byte instruction code, thus returning to normal operation. a ?continuous read mode? reset command can also be used to reset (m7 - 0) before issuing normal commands (see continuous read mode reset (ffh or ffffh)). figure 12 dual i/o f ast read sequence diagram (previous command set m5 - 4 =10) figure 12 quad i/o fast read (ebh) see figure 13, t he quad i/o fast read instruction is similar to the dual i/o fast read instruction but with the capability to input the 3 - byte address (a2 3 - 0) and a ?continuous read mode? byte and 4 - dummy clock 4 - bit per clock by io0, io1, io3, io4, each bit being latched in during the rising edge of sclk, then the memory contents are shifted out 4 - bit per clock cycle from io0, io1, io2, io3. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the quad enable bit (qe) of status register must be set to enable for the quad i/o fast read instruction. figure 13 quad i/o fast read sequence diagram (initial command or previous m5 - 4 10) figure 13
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 24 quad i/o fast read with ?continuous read mode? see figure 14, t he fast read quad i/o command can further reduce instruction overhead through setting the ?continuous read mode? bits (m7 - 0) after the input address bits (a23 - 0) , the up per nibble of the (m7 - 4) controls the length of the next fast read quad i/o command through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3 - 0) are don?t care (?x?). however, the io pins should be high - impedan ce prior to the falling edge of the first data out clock. if the ?continuous read mode? bits m5 - 4 = (1,0), then the next fast read quad i/o command (after /cs is raised and then lowered) does not require the ebh instruction code, this reduces the command s equence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the ?continuous read mode? bits m5 - 4 do not equal to (1,0), the next command (after /cs is raised and then lowered) requires the first byte instruct ion code, thus returning to normal operation. a ?continuous read mode? reset command can also be used to reset (m7 - 0) before issuing normal commands (see continuous read mode reset (ffh or ffffh)). figure 14 quad i/o fast read sequence diagram (previous c ommand set m5 - 4 =10) figure 14
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 25 continuous read mode reset (ffh or ffffh) t he ?continuous read mode? bits are used in conjunction with ?fast read dual i/o? and ?fast read quad i/o? instructions to provide the highest random flash memory ac cess rate with minimum spi instruction overhead, thus allowing more efficient xip (execute in place) with this device family. the ?continuous read mode? bits m7 - 0 are set by the dual/quad i/o read instructions. m5 - 4 are used to control whether the 8 - bit sp i instruction code (bbh or ebh) is needed or not for the next instruction. when m5 - 4 = (1,0), the next instruction will be treated the same as the current dual/quad i/o read instruction without needing the 8 - bit instruction code; when m5 - 4 do not equal to (1,0), the device returns to normal spi instruction mode, in which all instructions can be accepted. m7 - 6 and m3 - 0 are reserved bits for future use, either 0 or 1 values can be used. figure 15 t he continuous read mode reset instruction (ffh or ffffh) can b e used to set m4 = 1, thus the device will release the continuous read mode and return to normal spi operation. to reset ?continuous read mode? during quad i/o operation, only eight clocks are needed. the instruction is ?ffh?. to reset ?continuous read mod e? during dual i/o operation, sixteen clocks are needed to shift in instruction ?ffffh figure 15 continuous read mode reset sequence diagram figure 15
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 26 fast read quad i/o with ?8/16/32/64 - byte wrap around? the fast read quad i/o instruction can also be used to access a specific portion within a page by issuing a ?set burst with wrap? (77h) instruction prior to ebh. the ?set burst with wrap? (77h) instruction can either enable or disable the ?wrap around? feature for the following ebh instruct ions. when ?wrap around? is enabled, the data being accessed can be limited to either an 8,16, 32 or 64 - byte section of a 256 - byte page. the output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8 /16/32/64 - byte section, the output will wrap around to the beginning boundary automatically until /cs is pulled high to terminate the instruction. the burst with wrap feature allows applications that use cache to quickly fetch a critical address and then f ill the cache afterwards within a fixed length (8/16/32/64 - byte) of data without issuing multiple read instructions. the ?set burst with wrap? instruction allows three ?wrap bits?, w6 - 4 to be set. the w4 bit is used to enable or disable the ?wrap around? o peration while w6 - 5 are used to specify the length of the wrap around section within a page. similar to a quad i/o instruction, the set burst with wrap instruction is initiated by driving the /cs pin low and then shifting the instruction code ?77h? followe d by 24 dummy bits and 8 ?wrap bits?, w7 - 0. wrap bit w7 and the lower nibble w3 - 0 are not used. once w6 - 4 is set by a set burst with wrap instruction, all the following ?fast read quad i/o? and ?word read quad i/o? instructions will use the w6 - 4 setting to access the 8/16/32/64 - byte section within any page. to exit the ?wrap around? function and return to nor mal read operation, another set burst with wrap instruction should be issued to set w4=1. the default value of w4 upon power on is 1. table 9 w6 w5 w4 = 0 w4 = 1 (d ef a u l t ) w r ap a rou n d w r ap l e n gth w r a p a rou n d w r ap l e n gth 0 0 ye s 8 - byte no n/a 0 1 ye s 16 - byte no n/a 1 0 ye s 32 - byte no n/a 1 1 ye s 64 - byte no n/a figure 16 set burst with wrap command sequence figure 16
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 27 id and securi ty instructions read manufacture id/ device id (90h) see figure 17, t he read manufacturer/device id instruction is an alternative to the release from power - down/device id instruction that provides both the jedec assigned manufacturer id and the specific de vice id. the instruction is initiated by driving the /cs pin low and shifting the instruction code ?90h? followed by a 24 - bit address (a23 - a0) of 000000h. if the 24 - bit address is initially set to 000001h, the device id will be read first. figure 1 7 read manufacture id/ device id sequence diagram figure 17 jedec id (9fh) the jedec id instruction allows the 8 - bit manufacturer identification to be read, followed by two bytes of device identification. the device identification indicates the memory ty pe in the first byte, and the memory capacity of the device in the second byte. jedec id instruction while an erase or program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the jedec id instruction should not be issued while the device is in deep power - down mode. see figure 18, h e device is first selected by driving /cs to low. then, the 8 - bit instruction code for the instruction is shifted in. this is followed by the 24 - bit device identification, stored in the me mory, being shifted out on serial data output, each bit being shifted out during the falling edge of serial clock. the jedec id instruction is terminated by driving /cs to high at any time during data output. when /cs is driven high, the device is put in t he standby mode. once in the standby mode, the device waits to be selected, so that it can receive, decode and execute instructions. figure 18 jedec id sequence diagram figure 18
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 28 deep power - down (b9h) although the standby current during normal operation is relatively low, standby current can be further reduced with the deep power - down instruction. the lower power consumption makes the deep power - down (dpd) instruction especially useful for battery powered applications (see icc1 and icc2). the i nstruction is initiated by driving the /cs pin low and shifting the instruction code ?b9h? as shown in figure 19 the /cs pin must be driven high after the eighth bit has been latched. if this is not done the deep power down instruction will not be executed . after /cs is driven high, the power - down state will entered within the time duration of tdp. while in the power - down state only the release from deep power - down / device id instruction, which restores the device to normal operation, will be recognized. a ll other instructions are ignored. this includes the read status register instruction, which is always available during normal operation. ignoring all but one instruction also makes the power down state a useful condition for securing maximum write protect ion. the device always powers - up in the normal operation with the standby current of icc1. figure 19 deep power - down sequence diagram figure 19
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 29 release from deep power - down/read device id (abh) the release from power - down or device id instructi on is a multi - purpose instruction. it can be used to release the device from the power - down state or obtain the devices electronic identification (id) number. see figure 20 , t o release the device from the power - down state, the instruction is issued by dri ving the /cs pin low, shifting the instruction code ?abh? and driving /cs high release from power - down will take the time duration of tres1 (see ac characteristics) before the device will resume normal operation and other instruction are accepted. the /cs pin must remain high during the tres1 time duration. when used only to obtain the device id while not in the power - down state, the instruction is initiated by driving the /cs pin low and shifting the instruction code ?abh? followed by 3 - dummy byte. the dev ice id bits are then shifted out on the falling edge of sclk with most significant bit (msb) first as shown in see figure 21 the device id value for the ACE25Q400G is listed in manufacturer and device identification table. the device id can be read continu ously. the instruction is completed by driving /cs high. when used to release the device from the power - down state and obtain the device id, the instruction is the same as previously described, and shown in see figure 21, except that after /cs is driven hi gh it must remain high for a time duration of tres2 (see ac characteristics). after this time duration the device will resume normal operation and other instruction will be accepted. if the release from power - down/device id instruction is issued while an e rase, program or write cycle is in process (when wip equal 1) the instruction is ignored and will not have any effects on the current cycle. figure 2 0 release power - down sequence diagram figure 20 figure 2 1 release power - down/read device id seq uence diagram figure 21
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 30 read security registers (48h) see figure 22, t he read security registers instruction is similar to fast read instruction. the instruction is followed by a 3 - byte address (a23 - a0) and a dummy byte, each bit being latched - in during the rising edge of sclk. then the memory content, at that address, is shifted out on so, each bit being shifted out, at a max frequency fc, during the falling edge of sclk. the first byte addressed can be at any location. the address is automatic ally incremented to the next higher address after each byte of data is shifted out. once the a9 - a0 address reaches the last byte of the register (byte 3ffh), it will reset to 000h, the instruction is completed by driving /cs high table 10 a dd r e s s a2 3 - a 1 6 a1 5 - a8 a 7 - a0 se c urity r e gi st ers 1 00h 01h byte ad dre ss se c urity r e gi st ers 2 00h 02h byte ad dre ss se c urity r e gi st ers 3 00h 03h byte ad dre ss figure 22 read security registers instruction sequence diagram figure 2 2
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 31 erase securi ty registers (44h) the ACE25Q400G provides three 256 - byte security registers which can be erased and programmed individually. these registers may be used by the system manufacturers to store security and other important information separately from the main memory array. see figure 23, t he erase security registers instruction is similar to sector/block erase instruction. a write enable instruction must previously have been executed to set the write enable latch bit. the erase security registers instruction s equence: /cs goes low sending erase security registers instruction /cs goes high. /cs must be driven high after the eighth bit of the instruction code has been latched in otherwise the erase security registers instruction is not executed. as soon as /cs is driven high, the self - timed erase security registers cycle (whose duration is tse) is initiated. while the erase security registers cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in p rogress (wip) bit is 1 during the self - timed erase security registers cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch bit is reset. the security registers lock bit (lb) in the status regi ster can be used to otp protect the security registers. once the lb bit is set to 1, the security registers will be permanently locked; the erase security registers instruction will be ignored. table 11 a dd r e s s a2 3 - a 1 6 a1 5 - a8 a 7 - a0 se c urity r e gi st ers 1 00h 01h dont care se c urity r e gi st ers 2 00h 02h dont care se c urity r e gi st ers 3 00h 03h dont care figure 23, erase security registers instruction sequence diagram figure 2 3
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 32 program security registers (42h) see figure 24, t he program s ecurity registers instruction is similar to the page program instruction. it allows from 1 to 256 bytes security registers data to be programmed. a write enable instruction must previously have been executed to set the write enable latch bit before sending the program security registers instruction. the program security registers instruction is entered by driving /cs low, followed by the instruction code (42h), three address bytes and at least one data byte on si. as soon as /cs is driven high, the self - tim ed program security registers cycle (whose duration is tpp) is initiated. while the program security registers cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed program security registers cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch bit is reset. if the security registers lock bit (lb3/lb2/lb1) is set to 1, the security registers will be permanently locked. program security registers instruction will be ignored. table 12 a dd r e s s a2 3 - a 1 6 a1 5 - a8 a 7 - a0 se c urity r e g i s t ers 1 00h 01h byte ad dr e ss se c urity r e g i s t ers 2 00h 02h byte ad dr e ss se c urity r e g i s t ers 3 00h 03h byte ad dr e ss figure 24 program security registers instruction sequence diagram figure 24
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 33 program and erase instructions page program (02h) the page program instruction is for programming the memory. a write enable instruction must previously h ave been executed to set the write enable latch bit before sending the page program instruction. see figure 25, t he page program instruction is entered by driving /cs low, followed by the instruction code, three address bytes and at least one data byte on si. if the 8 least significant address bits (a7 - a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7 - a0) are all zero). /cs must be driven low for the entire duration of the sequence. the page program instruction sequence: /cs goes low sending page program instruction 3 - byte address on si at least 1 byte data on si /cs goes high. the instruction sequence is shown in figure16. if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly pr ogrammed at the requested addresses without having any effects on the other bytes of the same page. /cs must be driven high after the eighth bit of the last data byte has been latched in; otherwise the page progr am instruction is not executed. as soon as / cs is driven high, the self - timed page program cycle (whose duration is tpp) is initiated. while the page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit i s 1 during the self - timed page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch bit is reset. a page program instruction applied to a page which is protected by the block protect ( sec, tb, bp2, bp1, bp0) bits (see table 6 & 7 ) is not executed. figure 25 page program sequence diagram figure 25
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 34 sector erase (20h) the sector erase instruction is for erasing the all data of the chosen sector. a write enable instruction must previously have been executed to set the write enable latch bit. the sector erase instruction is entered by driving /cs low, followed by the instruction code, and 3 - address byte on si. any address inside the sector is a valid address for the sector er ase instruction. /cs must be driven low for the entire duration of the sequence. see figure 26, t he sector erase instruction sequence: /cs goes low sending sector erase instruction 3 - byte address on si /cs goes high. the instruction sequence is shown in fi gure18. /cs must be driven high after the eighth bit of the last address byte has been latched in; otherwise the sector erase instruction is not executed. as soon as /cs is driven high, the self - timed sector erase cycle (whose duration is tse) is initiated . while the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed sector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch bit is reset. a sector erase instruction applied to a sector which is protected by the block protect (sec, tb, bp2, bp1, bp0) bits (see table 6 & 7 ) is not executed. figure 2 6 sector erase sequence diagram figure 26
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 35 32kb block erase (52h) the 32kb block erase instruction is for erasing the all data of the chosen block. a write enable instruction must previously have been executed to set the write enable latch bit. the 32kb bl ock erase instruction is entered by driving /cs low, followed by the instruction code, and three address bytes on si. any address inside the block is a valid address for the 32kb block erase instruction. /cs must be driven low for the e ntire duration of th e sequence. see figure 27, t he 32kb block erase instruction sequence: /cs goes low sending 32kb block erase instruction 3 - byte address on si /cs goes high. the instruction sequence is shown in figure19. /cs must be driven high after the eighth bit of the l ast address byte has been latched in; otherwise the 32kb block erase instruction is not executed. as soon as /cs is driven high, the self - timed block erase cycle (whose duration is tbe) is initiated. while the block erase cycle is in progress, the status r egister may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed block erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch bit is reset. a 32kb block erase instruction applied to a block which is protected by the block protect (sec, tb, bp2, bp1, bp0) bits (see table 6 & 7 ) is not executed. figure 2 7 32kb block erase sequence diagram figure 27
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 36 64kb block er ase (d8h) the 64kb block erase instruction is for erasing the all data of the chosen block. a write enable instruction must previously have been executed to set the write enable latch bit. the 64kb block erase instruction is entered by driving /cs low, fol lowed by the instruction code, and three address bytes on si. any address inside the block is a valid address for the 64kb block erase instruction. /cs must be driven low for the entire duration of the sequence. see figure 28, the 6 4kb block erase instruc tion sequence: /cs goes low sending 64kb block erase instruction 3 - byte address on si /cs goes high. the instruction sequence is shown in figure20. /cs must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64k b block erase instruction is not executed. as soon as /cs is driven high, theself - timed block erase cycle (whose duration is tbe) is initiated. while the block erase cycle is in progress, the status register may be read to check the value of the write in p rogress (wip) bit. the write in progress (wip) bit is 1 during the self - timed block erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch bit is reset. a 64kb block erase instruction appl ied to a block which is protected by the block protect (sec, tb, bp2, bp1, bp0) bits (see table 6 & 7 ) is not executed. figure 28 64kb block erase sequence diagram figure 28
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 37 chip erase (60/c7h) the chip erase instruction sets all memory within the device to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the chip erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifti ng the instruction code ?c7h? or ?60h?. the chip erase instruction sequence is shown in figure 29. the /cs pin must be driven high after the eighth bit has been latched. if this is not done the chip erase instruction will not be executed. after /cs is d riv en high, t he self - timed chip erase instruction will commence for a time duration of tce. while the chip erase cycle is in progress, chip erase cycle is in progress, the read status register instruction may still be accessed to check the status of the wip b it. the wip bit is a 1 during the chip erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again. after the chip erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. t he chi p erase instruction will not be executed if any page is protected by the block protect (cmp, s ec, tb, bp2, bp1, and bp0) bits (see table 6 & 7 ) is not executed. figure 29 chip erase sequence diagram figure 29 era se / prog r am s u spen d ( 7 5 h) the erase/program suspend instruction allows the system to interrupt a sector or block erase operation, then read from or program data to any other sector. the erase/program suspend instruction also allows the system to interrupt a page program operation and then read from any other page or erase any other sector or block. the erase/program suspend instruction sequence is shown in figure 30. the w r i t e s t a t us r e g i st e r s i ns tr uc t i o n ( 01h) and erase i ns tr uc t i o n s ( 20h, d 8 h , c 7h, 60h, 44h) are not a l l o w ed du r i ng e r a se su spen d. e r ase s usp e nd i s va lid onl y dur i ng t he s ec t or or b l o ck e r ase operation. if written during the chip erase operation, the erase suspend instruction is ignored. the write status registers instruction (01h), and program instructions (02h, 42h) are not allowed during program suspend. program suspend is valid only during the page program operation. figure 30 erase/program suspend command sequence figure 30
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 38 erase / program resume (7ah) the erase/program resume instruction ?7ah? must be written to resume the sector or block erase operation or the page program operation after an erase/program suspend. the resume instruction ?7ah? will be accepted by the device only if the sus bit in the status register equals to 1 and the wip bit equals to 0. aft er the resume instruction is issued the sus bit will be cleared from 1 to 0 immediately, the wip bit will be set from 0 to 1 within 200 ns and the sector or block will complete the erase operation or the page will complete the program operation. if the sus bit equals to 0 or the wip bit equals to 1, the resume instruction ?7ah? will be ignored by the device. the erase/program resume instruction sequence is shown in figure 3 1 . figure 31 erase/program resume command sequence figure 31 reset device inst ructions enable reset (7eh) and reset device (99h) because of the small package and the limitation on the number of pins, the ACE25Q400G provides a software reset instruction instead of a dedicated reset pin. once the software reset instruction is accepte d, any on - going internal operations will be terminated and the device will return to its default power - on state and lose all the current volatile settings, such as volatile status register bits, write enable latch (wel) status, program/erase suspend status , continuous read mode bit setting (m7 - m0) and wrap bit setting (w6 - w4). to avoid accidental reset, both ?enable reset (7eh)? and ?reset (99h)? instructions must be issued in sequence. any other commands other than ?reset (99h)? after the ?enable reset (7 eh)? command will disable the ?reset enable? state. a new sequence of ?enable reset (7eh)? and reset (99h)? is needed to reset the device. once the reset command is accepted by the device, the device will take approximately 30us to reset. during this peri od, no command will be accepted. the enable reset (7eh) and reset (99h) instructio n sequence is shown in figure 32 . data corruption may happen if there is an on - going or suspended internal erase or program operation when reset command sequence is accepted by the device. it is recommended to check the busy bit and the sus bit in status register before issuing the reset command sequence. figure 32 reset (7eh) and reset (99h) command sequence figure 32
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 39 electrical characteristics table 13 absolute max imum ratings p a r a m e te r s sy m b o l c o nd i ti o n s r a n g e u n i t su p p l y v o l t age v c c C0 . 5 t o 4 v v o l t age ap p l i ed t o any p i n v i o r e l a t i v e t o gr ound C0 . 5 t o 4 v tran si e nt vo l t a ge on any p i n v io t <20ns transient relative to ground C2 . 0v t o v c c + 2 . 0 v v s t ora g e t e m pera t ure t s tg C 65 t o + 150 c e l ec tr os t a t i c d i sc h arge v o l t a g e v es d h u m an b ody m ode l (1) C200 0 t o + 2000 v notes: 1. jedec std jesd22 - a114a (c1=100pf, r1=1500 ohms, r2=500 ohms) operating ranges table 14 p ar a m e te r sy m b o l c o nd i ti o n s s pe c u n i t mi n ma x su p p l y v o l t age v c c fr = 108mhz, fr = 50mhz 2 . 7 3 . 6 v temperature operating ta commercial industrial - 40 +85 c d ata retention and endurance table 15 para m eter t est c o n d iti o n mi n u ni t s minimum pattern data retention time 150c 10 years 125c 20 years erase/program endurance - 40 to 85c 100k cycles
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 40 latch up characteristics table 16 parameter min max input voltage respect to vss on i/o pins - 1.0v vcc+1.0v vcc current - 100ma 100ma power - up timing symbol parameter min max unit tvsl vcc(min) to /cs low 10 us tpuw time delay from vcc(min) to write instruction 1 10 ms vwi write inhibit voltage vcc(min) 1 2.5 v figure 33 po wer - up timing and voltage levels figure 33
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 41 dc electrical characteristics (t= - 40 ~85 , vcc=2.7~3.6v) table 17 symbol parameter test condition min. typ max. unit. ili input leakage current 2 a ilo output leakage current 2 a icc1 standby current /cs=vcc, vin=vcc or vss 13 25 a icc2 deep power - down current /cs=vcc, vin=vcc or vss 2 5 a icc3 current: read single/dual/quad 1mhz sclk=0.1vcc/ 0.9vcc (1) 3/4/5 3.5/5/6 ma current: read single/dual/quad 33mhz 5/11/19 7.5/12/19.5 ma current: read single/dual/quad 50mhz 6.5/16/30 9.5/17/33 ma current: read single/dual/q uad 108mhz 10/33/60 12/35/65 ma icc4 operating current(page program) /cs=vcc 15 ma icc5 operating current(wrsr) /cs=vcc 5 ma icc6 operating current(sector erase) /cs=vcc 20 ma icc7 operating current(block erase) /cs=vcc 20 ma icc8 operating current (chip erase) /cs=vcc 20 ma vil input low voltage - 0.5 0.2vcc v vih input high voltage 0.8vcc vcc+0.4 v vol output low voltage iol =100a 0.4 v voh output high voltage ioh = - 100a vcc - 0.2 v note: (1) icc3 is measured with ate loading
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 42 ac measurement conditions ta b l e 18 symbol parameter min tpy max unit cl load capacitance 30 pf tr, tf input rise and fall time 5 ns vin input pause voltage 0.2vcc to 0.8vcc v in input timing reference voltage 0.3vcc to 0.7vcc v out ou tput timing reference voltage 0.5vcc v figure 34 a c m easur e m ent i/ o wa ve f o r m figure 34
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 43 ac electrical characteristics table 19 symbol parameter min. typ. max. unit. fc cloc k frequency for al l instructi ons, except read data(03h) dc. 108 mhz fr clock freq. read data instruction(03h) dc. 55 mhz tclh serial clock high time 4 ns tcll serial clock low time 4 ns tclch serial clock rise time (slew rate) 0.1 (1) v/ns tchcl serial clock fall time (slew rate) 0.1 (1) v/ns tslch /cs active setu p time 5 ns tchsh /cs active hold time 5 ns tshch /cs not active setup time 5 ns tchsl /cs not active hold time 5 ns tshsl /cs high time read/write 20 ns tshqz output disable time 6 ns tclqx output hold time 0 ns tdvch data in s etup time 2 ns tchdx data in hold time 2 ns thlch /hold low setup time (relative to clock) 5 ns thhch /hold high setup time (relative to clock) 5 ns tchhl /hold high hold time (relative to clock) 5 ns tchhh /hold low hold time (relative to c lock) 5 ns thlqz /hold low to high - z output 6 ns thhqx /hold low to low - z output 6 ns tclqv clock low to output valid 7 ns twhsl write protect setup time before /cs low 20 ns tshwl write protect hold time after /cs high 100 ns tdp /cs hig h to deep power - down mode 0.1 s tres1 /cs high to standby mode without electronic signature read 3 s tres2 /cs high to standby mode with electronic signature read 1.5 s tsus /cs high to next instruction after suspend 2 s tw write status reg ister cycle time 10 15 (2) ms tbp1 byte program time (first byte) (3) 5 10 s tbp2 additional byte program time (after first byte) (3) 2.8 5 s tpp page programming time 0.7 2.4 ms tse sector erase time 60 300 ms tbe block erase time(32k bytes/64k bytes) 0.3/0.5 0.75/1.5 s tce chip erase time 4 1 0 s note: 1. tested with clock frequency lower than 50 mhz. 2. tw can be up to 45 ms at - 40 during the characterization of the current design. it will be improved in the future design. 3. for multiple bytes after first byte within a page, tbpn = tbp1 + tbp2 * n, where n is the number of bytes programmed .
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 44 figure 35 serial input timing figure 35 figure 36 output timing figure 36 figure 37 hold timing figure 37
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 45 packaging information uson8 3*2 (0. 7 5mm - 0.50mm) symbol mm min nom max a 0 .70 0. 7 5 0. 8 0 a1 0.02 0.05 b 0.18 0.25 0.30 c 0.118 0.20 0.25 d 1.90 2.00 2.10 d 2 1.40 1.50 1.60 e 2.90 3.00 3.10 e 2 1.50 1.60 1.70 e 0.50bsc nd 1.50bsc h 0.20 0.25 0.30 l 0.30 0.40 0.50
ace25q 4 00g 4 m bit spi nor flas h memory serie s ver 1. 2 46 notes ace does not assume any responsibility for use as critical components in life support devices or systems without the express written approval of the president and general counsel of ace e lectronics co., ltd. as sued herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and shoes failure to perform when properly used in accordance with instr uctions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the fa ilure of the life support device or system, or to affect its safety or effectiveness. ace technology co., ltd. http://www.ace - ele.com/

▲Up To Search▲

Price & Availability of ACE25Q400G

	To Download ACE25Q400G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .